This invention relates to a circuit structure of multiple dynamic registers used for image signal processing, and more particularly to a semiconductor integrated circuit including dynamic registers, which can contribute to structural simplification and power saving of an image signal processor formed as an LSI, and to shortening the time required for testing the processor.
In most LSIs for image signal processing, registers occupy 1/3 or more of the whole circuit. Therefore, the circuit complexity of each register significantly influences the integration level of the LSI chip. Further, in general, it is extremely difficult to test the functions of the image signal processing LSI from the outside, since in the LSI, logic gates constituted of a combinational circuit and registers constituted of a sequential circuit are connected in a complicated manner.
In the prior art, a method for enabling automatic generation of test data for such LSIs by a computer is generally employed to increase the error detection rate of test data. In this method, at the LSI function test, registers incorporated therein are connected in chains by means of a control signal supplied from the outside of the LSI, so that they can be made scannable. Then, scan data is input from the outside to the LSI so that the sequential circuit, which shows complex transition of circuit states, can be processed as a combinational circuit for which test data can be prepared easily.
A static register is used as the conventional register for the image signal processing LSI, which is designed by an ASIC (Application Specific Integrated Circuit) technique. First, the circuit structure and the operation of a static nonscan register as an example of the static register will be described, which does not have a scanning function for facilitating the function test.
FIG. 1 shows a typical circuit structure of the conventional 1-bit static nonscan register. Specifically, the circuit structure comprises a nonscan register and a clock buffer for writing data into the nonscan register and reading data therefrom. The nonscan register consists of inverters 37-41 and clocked inverters 42-45. Each clocked inverter functions as an inverter when a clock with a value of "1" is input to the control terminal, and shows a high impedance state when a clock with a value of "0" is input thereto.
In FIG. 1, a clock is input through the input terminal CP of the clock buffer, an inverted clock (.phi. bar) for data writing is output from the inverter 40, and a clock .phi. for data reading is output from the inverters 40 and 41.
Data input through the data input terminal D of the static nonscan register is input to the inverter 37 when the clock with the value of "1" is input to the control terminal (.phi. bar) of the clocked inverter 42 (i.e., when the terminal (.phi. bar) of the clocked inverter 42 is at "1"). When the clocks with the values of "0" and "1" are input to the control terminal (.phi. bar) of the clocked inverter 42 and the control terminal .phi. of the clocked inverter 43, respectively (i.e., when the terminals (.phi. bar) and .phi. of the clocked inverters 42 and 43 are at "0" and "1", respectively), the data input to the inverter 37 is held in it, which means that the register is in a written state.
Then, when the control terminal .phi. of the clocked inverter 44 is shifted to "1", the written data is read out from the output terminal Q of the register via the clocked inverter 44 and the inverter 38 and simultaneously transferred to the inverter 39. When the control terminal .phi. of the clocked inverter 44 and the control terminal (.phi. bar) of the clocked inverter 45 are at "0" and "1", respectively, the read data is held.
The 1-bit static nonscan register shown in FIG. 1 is characterized in that the clock buffer is included in a region enclosed with the broken line, and located near the nonscan register, and also that the nonscan register has twenty-six transistors and each of the outputs of the terminals .phi. and (.phi. bar) of the clock buffer drives four of the transistors.
The circuit structure and the operation of a static scan register with a scanning function for facilitating the function test will now be described.
FIG. 2 shows a typical circuit structure of the conventional 1-bit static scan register. Specifically, the circuit structure comprises a scan register, a clock buffer and a clock buffer for scanning. The scan register consists of inverters 46-54, clocked inverters 55-59 and transfer gates 60 and 61.
In FIG. 2, when a clock is input through the input terminal CP of the clock buffer, an inverted clock (.phi. bar) for data writing is output from the inverter 51, and a clock .phi. for data reading is output from the inverters 51 and 52. Further, when a clock A for scanning is input through the input terminal A of the scanning clock buffer, a clock (A bar) for scan data writing is output from the inverter 53. The clock A is also used to hold the scan data. A clock B for scanning is used to read scan data.
The normal operation mode of the static scan register will be described. In the normal operation mode, clocks (A bar) and B are set at "0".
Data input through a terminal D is supplied to the inverter 46 when the control terminal (.phi. bar) of the clocked inverter 55 is at "1". Then, when the terminal (.phi. bar) of the inverter 55 is shifted to "0", and the control terminal .phi. of the transfer gate is simultaneously shifted to "1" and hence turned on, the data supplied to the inverter 46 is written and held in it since at this time, the control terminal A of the clocked inverter 58 is at "1".
When the control terminal .phi. of the clocked inverter 56 is at "1", the written data is read out through the output terminal Q via the clocked inverter 56 and the inverter 47 and simultaneously transferred to the inverter 48. When the control terminal (.phi. bar) of the clocked inverter 59 is at "1", the data transferred to the inverter 48 is held in it. Since at this time, the control terminal B of the transfer gate 61 is at "0", the data is not output to a scan data output terminal SO.
The scan test mode of the scan register will be described. In FIG. 2, scan data input to a scan data input terminal SI is supplied to the inverter 46 when the control terminal (A bar) of the clocked inverter 57 and the control terminal .phi. of the transfer gate 60 are at "1". When the control terminal A of the clocked inverter 58 is at "1", the writing state is maintained.
When the control terminal .phi. of the clocked inverter 56 and the control terminal B of the transfer gate 61 are at "1", the written scan data is read through the scan data output terminal SO via the clocked inverter 56, the inverters 48 and 49, the transfer gate 61 and the inverter 50, and also through the output terminal Q via the inverter 47. When the terminal (.phi. bar) of the clocked inverter 59 is at "1", the read scan data is held in it.
The 1-bit static scan register shown in FIG. 2 is characterized in that two clock buffers are located near the register as indicated by the broken line, that the number of transistors incorporated in the register is increased to as many as forty-two in accordance with the addition of a function for scanning the register, and that the clock buffers drive eight transistors in total as in the aforementioned static scan register.
Thus, making the static register, which is used in the conventional LSI for image signal processing, have a scanning function inevitably increases the complexity and hence the chip size of the LSI as explained with reference to FIG. 2. This makes it difficult to reduce its manufacturing cost.
Since as described above, multiple static scan registers, which are employed in the conventional image signal processing LSI, have a complicated structure, the chip size required for the LSI is inevitably large, which prevents reduction of cost. The prior art cannot satisfy recent demands for reducing the cost and power consumption of the LSI and also the time required for testing it.